1 of 11 080299 features integrates nv sram, real time clock, crystal, power-fail control circuit and lithium energy source clock registers are accessed identically to the static ram. these registers are resident in the eight top ram locations totally nonvolatile with over 10 years of operation in the absence of power access time of 120 ns and 150 ns bcd coded year, month, date, day, hours, minutes, and seconds with leap year compensation valid up to 2100 power-fail write protection allows for 10% v cc power supply tolerance ds1646 only (dip module) - standard jedec byte-wide 128k x 8 ram pinout ds1646p only (powercap module board) - surface mountable package for direct connection to powercap containing battery and crystal - replaceable battery (powercap) - power-fail output - pin-for-pin compatible with other densities of ds164xp timekeeping ram ordering information ds1646-xxx 32-pin dip module -120 120 ns access -150 150 ns access *ds1646p-xxx 34-pin powercap module board -120 120 ns access -150 150 n s access *ds9034pcx power cap (required; must be ordered separately) pin assignment ds1646/ds1646p nonvolatile timekeeping ram www.dalsemi.com 1 nc 2 3 a15 a16 pfo v cc we oe ce dq7 dq6 dq5 dq4 dq3 dq2 dq1 dq0 gnd 4 5 6 7 8 9 10 11 12 13 14 15 16 17 nc a14 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 a13 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 34 nc x1 gnd v bat x2 34-pin powercap module board (uses ds9034pcx powercap) 13 1 2 3 4 5 6 7 8 9 10 11 12 14 31 32-pin encapsulated package a14 a7 a5 a4 a3 a2 a1 a0 dq1 dq0 v cc a15 nc we a13 a8 a9 a11 oe a10 ce dq7 dq5 dq6 32 30 29 28 27 26 25 24 23 22 21 19 20 a16 a12 a6 nc dq2 gnd 15 16 18 17 dq4 dq3
2 of 11 080299 pin description a0-a16 - address input ce - chip enable oe - output enable we - write enable v cc - +5 volts gnd - ground dq0-dq7 - data input/output nc - no connection pfo - power-fail output (ds1646p only) x1, x2 - crystal connection v bat - battery connection description the ds1646 is a 128k x 8 nonvolatile static ram with a full-function real time clock, which are both accessible in a byte-wide format. the nonvolatile timekeeping ram is functionally equivalent to any jedec standard 128k x 8 sram. the device can also be easily substituted for rom, eprom and eeprom, providing read/write nonvolatility and the addition of the real time clock function. the real time clock information resides in the eight uppermost ram locations. the rtc registers contain year, month, date, day, hours, minutes, and seconds data in 24-hour bcd format. corrections for the day of the month and leap year are made automatically. the rtc clock registers are double-buffered to avoid access of incorrect data that can occur during clock update cycles. the double-buffered system also prevents time loss as the timekeeping countdown continues unabated by access to time register data. the ds1644 also contains its own power-fail circuitry, which deselects the device when the v cc supply is in an out-of- tolerance condition. this feature prevents loss of data from unpredictable system operation brought on by low v cc as errant access and update cycles are avoided. packages the ds1644 is available in two packages: 32-pin dip and 34-pin powercap module. the 32-pin dip style module integrates the crystal, lithium energy source, and silicon all in one package. the 34-pin powercap module board is designed with contacts for connection to a separate powercap (ds9034pcx) that contains the crystal and battery. this design allows the powercap to be mounted on top of the ds1646p after the completion of the surface mount process. mounting the powercap after the surface mount process prevents damage to the crystal and battery due to the high temperatures required for solder reflow. the powercap is keyed to prevent reverse insertion. the powercap module board and powercap are ordered separately and shipped in separate containers. the part number for the powercap is ds9034pcx. clock operations - reading the clock while the double-buffered register structure reduces the chance of reading incorrect data, internal updates to the ds1646 clock registers should be halted before clock data is read to prevent reading of data in transition. however, halting the internal clock register updating process does not affect clock accuracy. updating is halted when a 1 is written into the read bit, the 7th most significant bit in the control register. as long as 1 remains in that position, updating is halted. after a halt is issued, the registers reflect the count, that is day, date, and time that was current at the moment the halt command was issued. however, the internal clock registers of the double-buffered system continue to update so that the clock accuracy is not affected by the access of data. all of the ds1646 registers are updated simultaneously after the clock status is reset. updating is within a second after the read bit is written to 0.
3 of 11 080299 block diagram ds1646 figure 1 truth table ds1646 table 1 v cc ce oe we mode dq power v ih x x deselect high-z standby x x x deselect high-z standby v il x v il write data in active v il v il v ih read data out active 5 volts 10% v il v ih v ih read high-z active <4.5 volts >v bat x x x deselect high-z cmos standby 4 of 11 080299 clock accuracy (dip module) the ds1646 is guaranteed to keep time accuracy to within 1 minute per month at 25 c. clock accuracy (powercap module) the ds1646p and ds9034pcx are each individually tested for accuracy. once mounted together, the module is guaranteed to keep time accuracy to within 1.53 minutes per month (35 ppm) at 25 c. ds1646 register map - bank1 table 2 data address b 7 b 6 b 5 b 4 b 3 b 2 b 1 b 0 function 1fff - - - - - - - - year 00-99 1ffe x x x - - - - - month 01-12 1ffd x x - - - - - - date 01-31 1ffc x ft x x x - - - day 01-07 1ffb x x - - - - - - hour 00-23 1ffa x - - - - - - - minutes 00-59 1ff9 osc - - - - - - - seconds 00-59 1ff8 w r x x x x x x control a osc = stop bit r = read bit ft = frequency test w = write bit x = unused note: all indicated ?x? bits are not dedicated to any particular function and can be used as normal ram bits. retrieving data from ram or clock the ds1646 is in the read mode whenever we (write enable) is high; ce (chip enable) is low. the device architecture allows ripple-through access to any of the address locations in the nvsram. valid data will be available at the dq pins within t aa after the last address input is stable, providing that the ce and oe access times and states are satisfied. if ce or oe access times are not met, valid data will be available at the latter of chip-enable access (t cea ) or at output enable access time (t oea ). the state of the data input/output pins (dq) is controlled by ce and oe . if the outputs are activated before t aa , the data lines are driven to an intermediate state until t aa . if the address inputs are changed while ce and oe remain valid, output data will remain valid for output data hold time (t oh ) but will then go indeterminate until the next address access. writing data to ram or clock the ds1646 is in the write mode whenever we and ce are in their active state. the start of a write is referenced to the latter occurring high to low transition of we and ce . the addresses must be held valid throughout the cycle. ce or we must return inactive for a minimum of t wr prior to the initiation of another read or write cycle. data in must be valid t ds prior to the end of write and remain valid for t dh afterward. in a typical application, the oe signal will be high during a write cycle. however, oe can be active provided that care is taken with the data bus to avoid bus contention. if oe is low prior to we transitioning low the data bus can become active with read data defined by the address inputs. a low transition on we will then disable the outputs t wez after we goes active.
5 of 11 080299 data retention mode when v cc is within nominal limits (v cc > 4.5 volts) the ds1646 can be accessed as described above with read or write cycles. however, when v cc is below the power-fail point v pf (point at which write protection occurs) the internal clock registers and ram are blocked from access. this is accomplished internally by inhibiting access via the ce signal. at this time the power-fail output signal ( pfo ) will be driven active low and will remain active until v cc returns to nominal levels. when v cc falls below the level of the internal battery supply, power input is switched from the v cc pin to the internal battery and clock activity, ram, and clock data are maintained from the battery until v cc is returned to nominal level.
6 of 11 080299 absolute maximum ratings* voltage on any pin relative to ground -0.3v to +7.0v operating temperature 0c to 70c storage temperature -20c to +70c soldering temperature 260c for 10 seconds (s ee note 7) * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. recommended dc operating conditions (0 c to 70 c) parameter symbol min typ max units notes supply voltage v cc 4.5 5.0 5.5 v 1 logic 1 voltage all inputs v ih 2.2 v cc +0.3 v logic 0 voltage all inputs v il - 0.3 0.8 v dc electrical characteristics (0 c t a 70 c; v cc =5.0v 10%) parameter symbol min typ max units notes average v cc power supply current i cc1 85 ma 2, 3 ttl standby current ( ce =v ih ) i cc2 3 6 ma 2, 3 cmos standby current ( ce =v cc -0.2v) i cc3 2 4.0 ma 2, 3 input leakage current (any input) i il -1 +1 m a output leakage current i ol -1 +1 m a output logic 1 voltage (i out = -1.0 ma) v oh 2.4 v output logic 0 voltage (i out = +2.1 ma) v ol 0.4 v write protection voltage v pf 4.0 4.25 4.5 v
7 of 11 080299 ac electrical characteristics (0 c to 70 c; v cc = 5.0v 10%) ds1251y-120 ds1251y-150 parameter symbol min max min max units notes read cycle time t rc 120 150 ns address access time t aa 120 150 ns ce access time t cea 120 150 ns ce data off time t cez 40 50 ns output enable access time t oea 100 120 ns output enable data off time t oez 40 50 ns output enable to dq low-z t oel 5 5 ns ce to dq low-z t cel 5 5 ns output hold from address t oh 5 5 ns write cycle time t wc 120 150 ns address setup time t as 0 0 ns ce pulse width t cew 100 120 ns address hold from end of write t ah1 t ah2 5 30 5 30 ns ns 5 6 write pulse width t wew 75 90 ns we data off time t wez 40 50 ns we or ce inactive time t wr 10 10 ns data setup time t ds 85 110 ns data hold time high t dh1 t dh2 0 25 0 25 ns ns 5 6 ac test conditions input levels: 0v to 3v transition times: 5 ns capacitance (t a = 25 c) parameter symbol min typ max units notes capacitance on all pins (except dq) c i 7 pf capacitance on dq pins c dq 10 pf ac electrical characteristics (power-up/down timing) (0 c to 70 c) parameter symbol min typ max units notes ce or we at v ih before power-down t pd 0 m s v pf (max) to v pf (min) v cc fall time t f 300 m s v pf (min) to v so v cc fall time t fb 10 m s v so to v pf (min) v cc rise time t rb 1 m s v pf (min) to v pf (max) v cc rise time t r 0 m s power-up t rec 15 25 35 ms expected data retention time (oscillator on) t dr 10 years 4
8 of 11 080299 ds1646 read cycle timing ds1646 write cycle timing
9 of 11 080299 power-down/power-up timing notes: 1. all voltages are referenced to ground. 2. typical values are at 25 c and nominal supplies. 3. outputs are open. 4. data retention time is at 25 c and is calculated from the date code on the device package. the date code xxyy is the year followed by the week of the year in which the device was manufactured. for example, 9225 would mean the 25 th week of 1992. output load 5. t ah1 , t dh1 are measured from we going high. 6. t ah2 , t dh2 are measured from ce going high. 7. real-time clock modules (dip) can be successfully processed through conventional wave-soldering techniques as long as temperatures as long as temperature exposure to the lithium energy source contained within does not exceed +85 c. post-solder cleaning with water washing techniques is acceptable, provided that ultrasonic vibration is not used. in addition, for the powercap version: a. dallas semiconductor recommends that powercap module bases experience one pass through solder reflow oriented with the label side up (?live-bug?). b. hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the
10 of 11 080299 part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder. ds1646 32-pin package pkg 28-pin dim min max a in. mm 1.670 38.42 1.690 38.93 b in. mm 0.715 18.16 0.740 18.80 c in. mm 0.335 8.51 0.365 9.27 d in. mm 0.075 1.91 0.105 2.67 e in. mm 0.015 0.38 0.030 0.76 f in. mm 0.140 3.56 0.180 4.57 g in. mm 0.090 2.29 0.110 2.79 h in. mm 0.590 14.99 0.630 16.00 j in. mm 0.010 0.25 0.018 0.45 k in. mm 0.015 0.38 0.025 0.64 ds1646p pkg inches dim min nom max a 0.920 0.925 0.930 b 0.980 0.985 0.990 c - - 0.080 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.025 0.027 0.030 note: for the powercap version: a. dallas semiconductor recommends that powercap module bas es experience one pass through solder reflow oriented with the label side up (?live - bug?). b. hand soldering and touch-up: do not touch or apply the soldering iron to leads for more than 3 seconds. to solder, apply flux to the pad, heat the lead frame pad and apply solder. to remove the part, apply flux, heat the lead frame pad until the solder reflows and use a solder wick to remove solder.
11 of 11 080299 ds1646p with ds9034pcx attached pkg inches dim min nom max a 0.920 0.925 0.930 b 0.955 0.960 0.965 c 0.240 0.245 0.250 d 0.052 0.055 0.058 e 0.048 0.050 0.052 f 0.015 0.020 0.025 g 0.020 0.025 0.030 recommended powercap module land pattern pkg inches dim min nom max a - 1.050 - b - 0.826 - c - 0.050 - d - 0.030 - e - 0.112 -
|
